Teaching FPGA Security

International audienceTeaching FPGA security to electrical engineering students is new at graduate level. It requires a wide field of knowledge and a lot of time. This paper describes a compact course on FPGA security that is available to electrical engineering master's students at the Saint-Etienne Institute of Telecom, University of Lyon, France. It is intended for instructors who wish to design a new course on this topic. The paper reviews the motivation for the course, the pedagogical issues involved, the curriculum, the lab materials and tools used, and the results. Details are provided on two original lab sessions, in particular, a compact lab that requires students to perform differential power analysis of FPGA implementation of the AES symmetric cipher. The paper gives numerous relevant references to allow the reader to prepare a similar curriculum

Des terminaux green reconfigurables - vers une électronique durable

Vers une électronique durable ..

A comparison of PUF cores suitable for FPGA devices

A PUF extracts a unique identifier per die using physical random variation caused by variability of the manufacturing process. PUFs can be used for hardware authentication, but also as generators of confidential keys. This paper presents the comparison of RO-PUF and TERO-PUF cores implemented on Xilinx Spartan 6 FPGA. The objective is to evaluate their design when operating at the same conditions. We show that no ideal PUF exists and therefore designers will always have to choose the PUF matching the security application. In addition to design parameters like area, number of bits per challenge and power consumption, we discuss the feasibility of the design in FPGAs. This will help designers select the best PUF according to their requirements

Functional Locking Modules for Design Protection of Intellectual Property Cores

International audienceElectronics systems design is increasingly uses Intellectual Property (IP) cores. The means, however, that can renderthe IP core unusable if it has been obtained illegally have not yet been identified. We describe lightweight locking schemes lacking in the state of the art

A Survey of hardware protection of design data for integrated circuits and intellectual properties

International audienceThis paper reviews the current situation regarding design protection in the microelectronics industry. Over the past ten years, the designers of integrated circuits and intellectual properties have faced increasing threats including counterfeiting, reverse-engineering and theft. This is now a critical issue for the microelectronics industry, mainly for fabless designers and intellectual properties designers. Coupled with increasing pressure to decrease the cost and increase the performance of integrated circuits, the design of a secure, efficient, lightweight protection scheme for design data is a serious challenge for the hardware security community. However, several published works propose different ways to protect design data including functional locking, hardware obfuscation, and IC/IP identification. This paper presents a survey of academic research on the protection of design data. It concludes with the need to design an efficient protection scheme based on several properties

SALWARE: Salutary Hardware to design Trusted IC.

Fabless semiconductor industries are facing the rise of design costs of integrated circuits. This rise is link to the technology change and the complexity increasing. It follows that integrated circuits have become targets of counterfeiting and theft. The SALWARE project aims to study (theoretically and experimentally) salutary hardware design in order to fight against theft, illegal cloning and counterfeiting of integrated circuits. Salutary hardware means an embedded hardware system, hardly detectable / circumvented, inserted in an integrated circuit or a virtual component (Intellectual Property), used to provide intellectual property information (eg watermarking or hardware license) and / or to remotely activate the circuit or IP after manufacture and during use

Automatic low-cost IP watermarking technique based on output mark insertions

International audienceToday, although intellectual properties (IP) and their reuse are common, their use is causing design security issues: illegal copying, counterfeiting, and reverse engineering. IP watermarking is an efficient way to detect an unauthorized IP copy or a counterfeit. In this context, many interesting solutions have been proposed. However, few combine the watermarking process with synthesis. This article presents a new solution, i.e. automatic low cost IP watermarking included in the high-level synthesis process. The proposed method differs from those cited in the literature as the marking is not material, but is based on mathematical relationships between numeric values as inputs and outputs at specified times. Some implementation results with Xilinx Virtex-5 FPGA that the proposed solution required a lower area and timing overhead than existing solutions

La sécurité des objets connectés : les défis matériels

International audienceCette présentation fait le point sur les défis matériels pour la sécurité des objets connectés

An ultra-lightweight transmitter for contactless rapid identification of embedded IP in FPGA

International audienceThis letter presents the first ultra-lightweight transmitter based on electromagnetic emanation to send embedded intellectual properties (IP) identity (ID) quickly and discreetly. The proposed solution is based on a binary frequency shift keying (BFSK) transmitter that ensures an exceptionally high data rate. In addition, we present a coherent demodulation method using slippery window spectral analysis to recover data outside the device. The hardware resources occupied by the transmitter represent less than 0.022% of a 130 nm Microsemi Fusion FPGA. The experimental bitrate of the data transmission is around 500 times higher than the bitrate available for other state of the art spy circuitry using power consumption. In comparison with other works, our proposal goes clearly towards using a spy circuit in an industrial context for IP protection

Reversible Denial-of-Service by Locking Gates Insertion for IP Cores Design Protection

International audienceNowadays, electronics systems design is a complex process. A design-and-reuse model has been adopted, and the vast majority of designers integrates third party intellectual property (IP) cores in their design in order to reduce time to market. Due to their immaterial form and high market value, IP cores are exposed to threats such as cloning and illegal copying. In order to fight these threats, we propose to achieve functional locking, equivalent to a triggerable and reversible denial-of-service. This is done by inserting locking gates at specific locations in the netlist, allowing to force outputs at a fixed value. We developed a new method based on graph exploration techniques for locking gates insertion. It selects candidate nodes ten thousand times faster than state-of-the-art fault analysis-based logic masking techniques. Methods are then compared on ISCAS'85 combinational benchmarks